The invention pertains to semiconductor devices and the fabrication thereof, and particularly to ruthenium- and tungsten-containing electrically conductive layers and the formation and use thereof.
A capacitor generally includes two electrical conductors in close proximity to, but separated from, each other. The two conductors form the xe2x80x9cplatesxe2x80x9d of the capacitor, and may be separated by a dielectric material. When a voltage is applied across the plates of a capacitor, electrical charge accumulates on the plates. If the plates are electrically isolated essentially immediately after a voltage is applied, the accumulated charge may be stored on the plates, thus xe2x80x9cstoringxe2x80x9d the applied voltage difference.
The fabrication of integrated circuits involves the formation of electrically conductive layers for use as various circuit components, including for use as capacitor plates. Memory circuits, such as DRAMs and the like, use electrically conductive layers to form the opposing plates of storage cell capacitors.
The drive for higher-performance, lower-cost integrated circuits dictates ever-decreasing area for individual circuit features, including storage capacitors. Since capacitance of a capacitor (the amount of charge that can be stored as a function of applied voltage) generally varies with the area of capacitor plates, as the circuit area occupied by the storage capacitor decreases, it is desirable to take steps to preserve or increase capacitance despite the smaller occupied area, so that circuit function is not compromised.
Various steps may be taken to increase or preserve capacitance without increasing the occupied area. For example, material(s) having higher dielectric constant may be used between the capacitor plates. Further, the plate surfaces may be roughened to increase the effective surface area of the plates without increasing the area occupied by he capacitor.
One method for providing a roughened surface for a plate of a storage cell capacitor is to form the plate of hemispherical grain polysilicon (HSG), possibly with an overlying metal layer. The hemispherical grains of HSG enhance the surface area of the plate without increasing its occupied area.
HSG presents difficulties in fabrication, however, because of the formation of silicon dioxide on and near the HSG. A silicon dioxide layer may form on the HSG, particularly during deposition of the capacitor""s dielectric layer. Even with an intervening metal layer present, oxygen from the deposition of the dielectric layer can diffuse through the metal layer, forming silicon dioxide at the polysilicon surface. Silicon diffusion through the metal layer may also produce a silicon dioxide layer between the metal and the dielectric layers.
Silicon dioxide between the metal layer and the HSG can degrade the electrical contact to the metal capacitor plate surface. Silicon dioxide between the metal layer and the dielectric layer can decrease the capacitance of the resulting capacitor.
To attempt to avoid these negative effects caused by formation of silicon dioxide, a diffusion barrier layer may be employed between the HSG and the metal layer. However, in the typical capacitor geometry, the greater the total number of layers, the larger the required minimum area occupied by the capacitor. Further, the upper surface of each additional layer deposited tends to be smoother than the underlying surface, reducing the increased surface area provided by an underlying rough layer.
While high-dielectric constant materials are known, many of these advantageous materials are formed with processes that are incompatible with other materials needed to form capacitors. For example, processes needed to form a particular dielectric layer can oxidize or otherwise impair the properties of the electrode layer on which the dielectric layer is to be formed. These processes can be incompatible because of the necessary process temperatures or process ambients.
For these reasons, improved materials and methods are needed for forming conducting layers, insulating layers, and capacitors using such layers.
The present invention provides improved conductive layers, dielectric layers, capacitors, methods for forming such layers, and capacitors using the layers.
In a representative embodiment, enhanced-surface-area (rough-surfaced) ruthenium containing electrically conductive layers are provided. These layers are compatible with high-dielectric-constant materials and are useful in the formation of integrated circuits, particularly for plates of storage capacitors in memory cells.
In one approach, the enhanced-surface-area electrically conductive layer may be formed by first forming a ruthenium oxide containing film or layer. The layer may be stoichiometric or non-stoichiometric, and may be amorphous or may have both ruthenium (Ru) and ruthenium oxide (RuO2) phases and may include other materials. The film may be formed, for example, by chemical vapor deposition techniques or by sputtering or any suitable techniques. The film may be formed over an underlying layer which may be electrically conductive.
The ruthenium oxide film may be processed at low pressure and high temperaturexe2x80x94generally at pressures at least about 75 torr or below, desirably about 20 torr or below, most desirably about 5 torr or belowxe2x80x94and at temperatures in the range of about 500 to 900xc2x0 C., desirably about 750 to about 850xc2x0 C.xe2x80x94so as to convert at least some of the ruthenium oxide to ruthenium and to yield a roughened ruthenium-containing layer with a mean grain size desirably in the range of about 100 Angstroms or larger.
The heating process, or anneal, is desirably performed in a non-oxidizing ambient. In an example embodiment, a nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the anneal. A nitrogen-supplying reducing ambient may be used to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. In another alternative, a nitrogen-supplying reducing ambient may be used in a post-anneal to passivate an already roughened layer. In still another alternative, a post-anneal in an oxidizing ambient may be performed, following either the roughening anneal or the nitride-passivation anneal, as desired. This oxidizing post-anneal provides oxygen to the roughened layer to reduce the tendency of the ruthenium to scavenge oxygen during later processing.
The enhanced-surface-area layer may be formed with or without a pre-anneal, performed at a higher pressure (such as about 600 torr), before the low pressure, high temperature anneal.
The roughened layer of ruthenium may be used to provide an enhanced-surface-area electrically conductive layer.
In an example embodiment, the roughened layer of ruthenium may be formed on an underlying electrically conductive layer, with the roughened layer and the underlying layer together functioning as an enhanced-surface-area electrically conductive layer.
In another example embodiment, an electrically conductive layer may be formed on or over the roughened layer, with the overlying electrically conductive layer and the roughened layer constituting an enhanced-surface area electrically conductive layer.
In either case, in an example capacitor embodiment for use in an integrated circuit, the resulting enhanced-surface-area electrically conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.
The ruthenium-containing enhanced-surface-area electrically conductive layer, particularly in the case of an anneal in nitrogen-supplying reducing ambient with an oxidizing post-anneal, has reduced tendency toward oxidation and is thus more compatible with the use of high-dielectric-constant dielectric materials, while still providing enhanced surface area. In addition, even if the ruthenium-containing layer oxidizes, it remains conductive. An additional metal layer thus may potentially be omitted from the capacitor structure, allowing smaller dimensions for capacitors with the same or even greater capacitance.
In an alternative embodiment, a tungsten nitride layer is provided as a first electrode layer. A dielectric layer and a second electrode layer are conformally applied to the first electrode layer to form a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed at an anneal temperature to increase the capacitance of the capacitor. In a specific embodiment, the anneal temperature is at least 500 C and the capacitor (or the tungsten nitride layer) is maintained at the anneal temperature for at least 30 seconds.
These methods, conductive and dielectric layers, and structures using the layers allow the design and fabrication of higher speed, higher density, and lower cost integrated circuits.